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document no. u18578ee1v0ds00 data published: june 2008 v850e/cag4-m 32-bit single-chip microcontroller the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. ? nec electronics 2008 datasheet mos integrated circuit pd70f3461 description this device is a new, powerful nec 32-bit risc microcontroller with embedded flexray communica- tion interface. with its high performance, large memory size and fully-fledged communication inter- faces it is especially well suited for high end gate way and other body applications in the automotive area. this microcontroller extends the widely used nec v850 family into the high performance range and supports with its flexray interface and the medialb? interface the upcoming new standards for communication inside automotive.it is optimized for gateway applications featuring control of up to 6 can as standard interfaces in the automotive area. with the embedded medialb? interface this device opens a new possibility to connect to the mo st? world, offering a ve ry high data throughput espc. for asynchronous data transfer. the timer stru cture is suitable for mo st body applications by offering high number of input capture and pwm out puts. the new multi lin master macro can connect all 6 lin channel in a very efficient way, with a minimum cpu interaction. with these features the device fits also to many body applications. ? 32-bit risc cpu with harvard architecture - floating point unit ? internal flash: 512 kb ? internal ram: 60 kb ? data flash: 32 kb ? advanced safety features - crc modul ? flexray: - bosch eray v.2.1 - 2 channel ? full-can interface: 6 channel ? 3-wire medialb interface ? multi lin master ? serial interfaces: 11 channels - 3-wire mode: 4 channels - uart mode: 6 channels (lin compatible) - i2c mode: 1 channel ? timers: 9 channels - 16-bit capture/compare timer: 7 channel - watch timer: 1 channel - window watchdog timer: 1 channel - motor control: 1 channel ? non multiplexed 16 bit businterface ? 10-bit resolution a/d converter: 10 channel ? i/o lines: 105 ? external interr upts: 15 + nmi ? power supply voltage range: - isolated area: +4.5v to +5.5v - main area: +3.0 v to +3.6 v ? frequencies: - main cpu frequency: 80 mhz - main osc: 16mhz - sub clock: 32khz - low-frequency internal oscillator: - 240khz (-50 / +100%) - high-speed internal oscillator: - 6.8 mhz ? power save mode support functionality ? temperature range: - -40c to +105c ? pd70f3461 ? package : - 144-pin plastic qfp, 0.5 mm pin-pitch (20 20 mm) ordering information device part number package flash ram v850e/cag4-m pd70f3461 lqfp144 20 20 mm 512 kb 60 kb feature
2 datasheet u18578ee1v0ds00 pd70f3461 internal block diagram of v850e/cag4-m - pd70f3461 bus control unit internal bus cpu core ports interrupt controller nmi intp0 to intp14 dma p00 to p07 p10 to p17 p20 to p27 p30 to p37 p40 to p46 p50 to p53 p60 to p63 p80 to p84 pcs0, pcs1, pcs3, pcs54 pct4 to pct6 pah0 to pah3 pal0 to pal15 pdh0 to pdh15 memory access serial interfaces 10-bit adc 10 channels ani00 to ani09 adtrg avdd avss avref measurement interface system controller program flash memory 512 kb iram 60 kb cpu reset flexray medialb fxenb frxdb fstpwt ftint0 ftxdb frxda ftxda ftxena mlbres mlberr txgain mlbclk mlbdat i2c sda0 scl0 csie0 to csie1 soe0 to soe1 sie0 to sie1 scke0 to scke1 scse00 to scse07 scse10 to scse13 sib0 to sib1 sckb0 to sckb1 sob0 to sob1 ssb1 brg uartd0 to uartd5 rxdd0 to rxdd5 txdd0 to txdd5 brg csib0 to csib1 brg crc module d0 to d15 a0 to a19 wait cs0, cs2, cs3, cs4 wrl rd 4 x 16-bit timer aa tiaa00 to tiaa30 tiaa01 to tiaa31 tevtaa0 to tevtaa3 ttrgaa0 to ttrgaa3 toaa00 to toaa30 toaa01 to toaa31 2 x 16-bit timer ab tiab01 to tiab11 tiab02 to tiab12 tiab03 to tiab13 tevtab0 to tevtab1 ttrgab0 to ttrgab1 motor control (tab0, taa0) toab0t1 to toab0t3 timers 16-bit timer m memory controller x2 main oscillator clock generator x1 auxiliary functions ddi ddo dck drst on-chip debug unit dms internal timer mlbsig power supply afcan0 to afcan4 fcrxd0 to fcrxd4 fctxd0 to fctxd4 multi lin master brg dafcan fcrxd5 fctxd5 fcrxd6 tiab00 to tiab10 toab00 to toab10 toab01 to toab11 toab02 to toab12 toab03 to toab13 window watchdog timer toab0b1 to toab0b3 watch timer (rtc) isolated area 32 x 16-bit general register wdtout power save mode support function regon sub oscillator (32 khz) xt2 xt1 internal oscillator (240 khz) data flash memory 32 kb wrh
3 datasheet u18578ee1v0ds00 pd70f3461 pin identification a00-a19 external memory interface address bus regc30-regc32 3v regulator output adtrg0 adc trigger input regc50 5v isolated area regulator output ani00-ani09 adc input regon isolated area power save mode control avdd adc power supply reset isolated area reset input avref adc reference voltage rxdd0-rxdd5 uartd0-uartd5 receive data avss analog ground sckb0-sckb1 serial interface csib0-csib1 clock line bvdd30-bvdd32 3v i/o port supply voltage scke0-scke1 serial interface csie0-csie1 clock line bvss30-bvss32 3v i/o port ground scsce00-scsce07 csie0 chip select bvss50 5v isolated area ground scsce10-scsce13 csie1 chip select cs0 -cs3 ext. memory interface chip select signals sib0-sib1 csib0-csib1 data input d00-d15 external memory interface data bus sie0-sie1 csie0-csie1 data input dck n-wire interface clock sob0-sob1 csib0-csib1 data output ddi n-wire i/f debug data input soe0-soe1 csie0-csie1 data output ddo n-wire interface debug data output ssb1 csib1 slave select input dms n-wire i/f debug mode select input tevtaa0-tevtaa3 timer taa0-taa3 event input drst n-wire debug interface reset tevtab0-tevtab1 timer tab0-tab1 event input error medialb external error status input tiaa00-tiaa30 timer taa00-taa30 capture trigger fcrx0-fcrx6 can0-can6 receive data tiaa01-tiaa31 timer taa01-taa31 capture trigger fctx0-fctx5 can0-can5 transmit data tiab00 - tiab03 timer tab0 capture trigger input flmd0 flash writing control tiab10 - tiab13 timer tab1 capture trigger input flmd1 mode control 1 toaa00-toaa30 timer taa00-taa30 pulse signal output frxda-frxdb flexray channel a&b receive data toaa01-toaa31 timer taa00-taa30 pulse signal output fstpwt interrupt signal from external flexray toab00- toab03 timer tab0 pulse signal output ftint0 interrupt signal from internal flexray toab10- toab13 timer tab1 pulse signal output ftxda-ftxdb flexray channel a&b transmit data toab0b1 - toab0b3 motor control ouput signal ftxena-ftxenb flexray channel a&b transmit perm. toab0t1 - toab0t3 motor control ouput signal icl iic clock ttrgaa0-ttrgaa3 timer taa0-taa3 trigger input idat iic data ttrgab0-ttrgab1 timer tab0-tab1 trigger input inicrst medialb reset output txdd0-txdd5 uartd0-uartd5 transmit data intp0-inp14 external interrupts txgain medialb fot txgain output mclk medialb clock input vdd30-vdd32 3v main supply voltage mdat medialb data vdd50 5v isolated area supply voltage mreset main area reset input vss30-vss32 3v main ground msig medialb signal vss50 5v isolated area ground mvdd memory interface power supply wait ext. memory interface data wait request mvss memory interface ground wdtout isolated area watchdog timer status nmi non-maskable interrupt wrh ext. memory interface write high strobe p60-p61 isolated area wake-up input wrl ext. memory interface write high strobe p62-p63 isolated area output x1-x2 main oscillator terminals rd external memory interface read strobe xt1-xt2 subclock oscillator terminals
4 datasheet u18578ee1v0ds00 pd70f3461 pin configuration ? 144-pin plastic lqfp (fine pitch) (20 mm 20 mm) (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 v850e/cag4-m mvss34 mvdd34 p60 / intp13 wdtout regon p62 avref p16 / msig p17 / mclk mvdd31 pdl2 / d02 p61 / intp14 p63 avdd avss ani00 ani01 ani02 ani03 ani04 ani05 ani06 ani07 ani08 ani09 p46 / intp0 / adtrg0 p01 / fctx0 p00 / fcrx0 p02 / fcrx1 p03 / fctx1 p04 / fcrx2 / txab00 p05 / fctx2 / txab01 / toab0b1 p06 / fcrx3 / txab02/ toab0b2 p07/fctx3/txab03/tevtab0/ttrgab0/toab0b3 bvdd30 bvss30 p10 / fcrx4 / tevtaa0 / txaa00 / toab0t1 p11 / fctx4 / ttrgaa0 / txaa01 / toab0t2 p12 / fcrx5 / toab0t3 p13 / fctx5 p14 / nmi p15 / mdat p40 / scke0 / error p41 / sie0 / inicrst / intp1 p42 / soe0 / txgain / intp2 p44 / sib1 / sda0 p43 / sckb1 / scl vdd31 vss31 regc31 p20 / ftint0 / sob1 / intp3 p21 / fstpwt / ssb1 / intp4 p22 / frxdb / intp5 bvdd31 bvss31 p23 / ftxdb / intp6 p24 / ftxenb / intp7 p25 / frxda p27 / ftxena p26 / ftxda p80 / drst / sib0 p81 / ddo / sob0 p82 / dck / sckb0 p83 / dms / rxdd0 p84 / ddi / txdd0 vdd32 vss32 regc32 pcs0 / cs0 pct4 / rd pct5 / wrl pct6 / wrh mvdd30 mvss30 pdl0 / d00 pdl1 / d01 pdl3 / d03 pdl4 / d04 pdl5 / d05 pdl6 / d06 pdl7 / d07 mvss31 pdl8 / d08 / tevtaa3 / txaa30 pdl9 / d09 / ttrgaa3 / txaa31 pdl10 / d10 / txab10 pdl11 / d11 / txab11 pdl12 / d12 / tevtab1 / txab12 pdl13 / d13 / ttrgab1 / txab13 pdl14 / d14 / scke1 pdl15 / d15 / sie1 mvdd32 mvss32 pal0 / a00 pal7 / a07 / scse00 pal6 / a06 / scse13 pal5 / a05 / scse12 pal4 / a04 / scse11 pal3 / a03 / scse10 pal2 / a02 / soe1 pal1 / a01 mvdd33 mvss33 pal8 / a08 / scse01 pal15 / a15 / rxdd5 pal14 / a14 / scse07 pal13 / a13 / scse06 pal12 / a12 / scse05 pal11 / a11 / scse04 pal10 / a10 scse03 pal9 / a09 / scse02 pah3 / a19 / intp10 pah2 / a18 / intp9 pah1 / a17 / intp8 pah0 / a16 / txdd5 p50 / tevtaa1 / txaa10 pcs1 / cs1/flmd1 p31 / rxdd4 p30 / txdd4 / wait p45 / fcrx6 / intp11 p53 / ttrgaa2 / txaa21 / cs3 p52 / tevtaa2 / txaa20 p51 / ttrgaa1 / txaa11 / cs2 vss30 vdd30 bvss32 bvdd32 regc30 flmd0 mreset x1 x2 bvss50 p32 / txdd1 p37 / rxdd3 / intp12 p36 / txdd3 p35 / rxdd2 p34 / txdd2 p33 / rxdd1 vss50 vdd50 regc50 xt1 xt2 reset isolated area
5 datasheet u18578ee1v0ds00 pd70f3461 pin functions port group name port name alternative outputs alternative inputs pin group pin location 6 a p60 - p60 / intp13 10 1 p61 - p61 / intp14 2 a wdtout - 3 regon - 4 6 a p62 p62 - 5 p63 p63 - 6 - avss 7 - avdd 8 - avref 9 -ani09 8 10 -ani0811 -ani0712 -ani0613 -ani0514 -ani0415 -ani0316 -ani0217 -ani0118 -ani0019 4 p46 - aadtrg0 / intp0 1a 20 0 p00 - fcrx0 21 p01 fctx0 - 22 p02 - fcrx1 23 p03 fctx1 - 24 p04 toab00 fcrx2 / tiab00 25 p05 fctx2 / toab01 / toab0b1 tiab01 26 p06 toab02 / toab0b2 fcrx 3 / tiab02 / tevtab0 27 p07 fctx3 / toab03 / toab0b3 tiab03 / ttrgab0 28 - bvdd30 29 - bvss30 30 1 p10 toaa00 / toab0t1 fcrx4 / tiaa00 / tevtaa0 1a 31 p11 fctx4 / toaa01 / toab0t2 tiaa01 / ttrgaa0 32 p12 toab0t3 fcrx5 33 p13 fctx5 - 34 p14 - nmi 35 p15 mdat mdat 2 36 p16 msig msig 37 p17 - mclk 38
6 datasheet u18578ee1v0ds00 pd70f3461 4 p40 scke0 scke0 / error 1b 39 p41 inicrst sie0 / intp1 40 p42 soe0/txgain intp2 41 p43 sckb1 / icl icl 42 p44 idat sib1 / idat 43 - vdd31 44 regc31 - 45 -vss3146 2 p20 sob1 ftint0 / intp3 3 47 p21 - fstpwt / ssb1 / intp4 48 p22 - frxdb / intp5 49 - bvdd31 50 - bvss31 51 2 p23 ftxdb intp6 3 52 p24 ftxenb intp7 53 p25 - frxda 54 p26 ftxda - 55 p27 ftxena - 56 8 p80 b - drst / sib0 6 57 p81 ddo / sob0 - 1b 58 p82 sckb0 dck / sckb0 59 p83 - dms / rxdd0 60 p84 txdd0 ddi 61 - vdd32 62 regc32 - 63 -vss3264 cs pcs0 cs0 - 5a 65 ct pct4 rd -66 pct5 wrl -67 pct6 wrh -68 - mvdd30 69 - mvss30 70 dl pdl0 d00 d00 5a 71 pdl1 d01 d01 72 pdl2 d02 d02 73 pdl3 d03 d03 74 pdl4 d04 d04 5b 75 pdl5 d05 d05 76 pdl6 d06 d06 77 pdl7 d07 d07 78 port group name port name alternative outputs alternative inputs pin group pin location
7 datasheet u18578ee1v0ds00 pd70f3461 -mvdd3179 - mvss30 80 dl pdl8 d08 / toaa30 d08 / tiaa30 / tevtaa3 5b 81 pdl9 d09 / toaa31 d09 / tiaa31 / ttrgaa3 82 pdl10 d10 / toab10 d10 / tiab10 83 pdl11 d11 / tiab11 d11 / toab11 84 pdl12 d12 / toab12 d12 / tiab12 / tevtab1 5c 85 pdl13 d13 / toab13 d13 / tiab13 / ttrgab1 86 pdl14 d14 / scke1 d14 / scke1 87 pdl15 d15 d15 / sie1 88 -mvdd3289 - mvss32 90 al pal0 a00 - 5c 91 pal1 a01 - 92 pal2 a02 / soe1 - 93 pal3 a03 / scse10 - 94 pal4 a04 / scse11 - 5d 95 pal5 a05 / scse12 - 96 pal6 a06 / scse13 - 97 pal7 a07 / scse00 - 98 -mvdd3399 - mvss33 100 al pal8 a08 / scse01 - 5d 101 pal9 a09 / scse02 - 102 pal10 a10 / scse03 - 103 pal11 a11 / scse04 - 104 pal12 a12 / scse05 - 5e 105 pal13 a13 / scse06 - 106 pal14 a14 / scse07 - 107 pal15 a15 rxdd5 108 -mvdd34109 - mvss34 110 ah pah0 a16 / txdd5 - 5e 111 pah1 a17 intp8 112 pah2 a18 intp9 113 pah3 a19 intp10 114 cs pcs1 cs1 flmd1 115 5 p50 toaa10 tiaa10 / tevtaa1 1c 116 p51 toaa11 / cs2 tiaa11 / ttrgaa1 117 p52 toaa20 tiaa2 0 / tevtaa2 118 p53 toaa21 / cs3 tiaa21 / ttrgaa2 119 port group name port name alternative outputs alternative inputs pin group pin location
8 datasheet u18578ee1v0ds00 pd70f3461 4 p45 - intp11 / fcrx6 1c 120 3 p30 txdd4 wait 121 p31 - rxdd4 122 - vdd30 123 regc30 - 124 -vss30125 -x1 7 126 -x2127 -mreset 4128 - bvdd32 129 - bvss32 130 3 p32 txdd1 - 1c 131 p33 - rxdd1 132 p34 txdd2 - 133 p35 - rxdd2 134 p36 txdd3 - 135 p37 - rxdd3 / inpt12 136 a - flmd0 13 137 - vdd50 138 regc50 - 139 - vss50 140 - xt1 12 141 - xt2 142 - reset 11 143 - bvss50 144 a. grey marked cells are located on the isolated area b. p80 is an input only pin port group name port name alternative outputs alternative inputs pin group pin location
9 datasheet u18578ee1v0ds00 pd70f3461
10 datasheet u18578ee1v0ds00 pd70f3461 table of contents 1. electrical specification : general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1.1 injected current absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.2 capacitance connected to regcx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.3 i/o capactitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2. electrical specification : device clock specifications . . . . . . . . . . . . . . . . 16 2.1 main oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 sub-oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 peripheral pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 cpu pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 low-frequency internal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6 high-frequency internal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.7 cpu clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.8 pll clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3. electrical specification : dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 general dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 input/output level of pin groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.1 input/output level pin group 1: main area general purpose ports . . . . . . . . . . . 21 3.2.2 input/output level pin group 2: medialb ports. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.3 input/output level pin group 3: flexray ports . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.4 input/out put level pin group 4: mreset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.5 input/output level pin group 5: external bus interface ports . . . . . . . . . . . . . . . . 22 3.2.6 input/output level pin group 6: input-only port p80. . . . . . . . . . . . . . . . . . . . . . . 23 3.2.7 input/output level pin group 10: isolated area general purpose ports . . . . . . . . 23 3.2.8 input/output level pin group 11 : isolated reset pin. . . . . . . . . . . . . . . . . . . . . . 24 3.2.9 input/output level pin group 13: isolated area flmd0 . . . . . . . . . . . . . . . . . . . . 24 3.3 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.4 injected current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.4.1 dc characteristics of overload current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.2 a/d converter influenced by injected curren t on adjacent pin . . . . . . . . . . . . . . . 25 4. electrical specification : ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . 26 4.1 reset of main area: mreset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 reset of isolated area: reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 interrupt timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.4 clocked serial interface b (csib) characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.5 enhanced queued clocked serial interface (csie) timing . . . . . . . . . . . . . . . . . . . . 34 4.6 i 2 c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.7 uartd timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 4.8 can timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.9 flexray timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 4.10 medialb timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 4.11 timer aa timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 4.12 timer ab timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 5. electrical specification : ad converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11 datasheet u18578ee1v0ds00 pd70f3461 6. electrical specification : flash memory characteristics . . . . . . . . . . . . . . 49 6.1 code flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.1 code flash general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.2 code flash self-programming characteristics ov er lifetime . . . . . . . . . . . . . . . . . 49 6.1.3 code flash end-of-line on-board progra mming characteristics (pg-fp4: csi) . 50 6.1.4 code flash end-of-line self-p rogramming characteristics . . . . . . . . . . . . . . . . . . 50 6.2 data flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2.1 data flash general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2.2 data flash self-programming characteristics over lifetime . . . . . . . . . . . . . . . . . 51 6.2.3 data flash end-of-line on-board progra mming characteristics (pg-fp4: csi). . 52 6.2.4 data flash end-of-line self-programming charac teristics . . . . . . . . . . . . . . . . . . 52 7. requirements for a supply voltage v dd50 below 4.5v . . . . . . . . . . . . . . . . 53 8. package drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
12 datasheet u18578ee1v0ds00 pd70f3461 1. electrical specifi cation : general 1.1 absolute maximum ratings t a = -40 ~ 105c, operation modes: all duration: 15years v ss5x = cv ss = v ss3x = av ss0 = mv ss3x = 0v table 1-1: absolute maximum ratings (1/2) parameter symbol test conditions ratings unit supply voltage v dd50 -0.5 to +6.5 v v dd3x -0.5 to +4.6 v av dd -0.5 to +4.6 v av ref -0.5 to +4.6 v mv dd3 -0.5 to +4.6 v bv dd3 -0.5 to +4.6 v av ss -0.5 to +0.5 v bv ss3 -0.5 to +0.5 v bv ss5 -0.5 to +0.5 v mv ss3 -0.5 to +0.5 v input voltage group 1 to 4, 6 v i1 v i1 < bv dd3 +0.5v -0.5 to +4.6 v group 5 v i5 v i5 < mv dd3 +0.5v -0.5 to +4.6 v group 10, 11, 13 v iia v iia < v dd5 +0.5v -0.5 to +6.5 v analog input voltage group 8 v iad v iad < av dd +0.3v v iad < av ref +0.3v v iad > av ss -0.3v -0.5 to +4.6 v output voltage group 1 to 8 v o1 -0.5 to +4.6 v group 10 v o2 -0.5 to +6.5 v operating ambient temperature t a normal operating mode -40 to +105 c storage temperature t stgb -40 to +125 c
13 datasheet u18578ee1v0ds00 pd70f3461 high level output current group 1 i oh13 1 pin -3.0 ma group 1a i oha1a total -20 ma group 1b i oha1b total -20 ma group 1b i oha1c total -20 ma group 2 i oh2 1 pin -6.0 ma groups 1a & 2 i oha1a2 total -20.0 ma group 3 i oh3 1 pin -3 ma groups 1b & 3 i oha1b3 total -20 ma groups 1,2 & 3 i oha123 total -60 ma groups 5 i oh5 1 pin -3 ma group 5a i oha5a total -20 ma group 5b i oha5b total -20 ma group 5c i oha5c total -20 ma group 5d i oha5d total -20 ma group 5e i oha5e total -20 ma group 5 i oha5 total -100 ma group 10 i oh10 1 pin -3 ma group 10 i oha10 total -20 ma low level output current group 1 i ol13 1 pin 3.0 ma group 1a i ola1a total 20 ma group 1b i ola1b total 20 ma group 1b i ola1c total 20 ma group 2 i ol2 1 pin 6.0 ma groups 1a & 2 i ola1a2 total 20.0 ma group 3 i ol3 1 pin 3 ma groups 1b & 3 i ola1b3 total 20 ma groups 1,2 & 3 i ola123 total 60 ma groups 5 i ol5 1 pin 3 ma group 5a i ola5a total 20 ma group 5b i ola5b total 20 ma group 5c i ola5c total 20 ma group 5d i ola5d total 20 ma group 5e i ola5e total 20 ma group 5 i ola5 total 100 ma group 10 i ol10 1 pin 3 ma group 10 i ola10 total 20 ma table 1-1: absolute maximum ratings (2/2) parameter symbol test conditions ratings unit
14 datasheet u18578ee1v0ds00 pd70f3461 cautions: 1. do not directly connect output (or i/o) pins of ic products to each other, or to v dd , v ss , and gnd. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any paramete r. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso- lute maximum ratings are not exceeded. the ratings and conditions shown below for dc characteristics and ac characteristics are within the range for normal operation and quality assurance. 1.1.1 injected current absolute maximum ratings t a =-40 to +105c cautions: 1. the total current includes the ouput current. 2. product quality may suffer if the absolute maximum ratings are exceeded even momentarily for any parameter. table 1-2: injected current: abdolute maximum ratings parameter symbol conditions min. typ. max. unit positive overload current v in > xv ddnx a a. xv ddnx : either bv dd3x with x = 0 to 2, mv dd3x with x = 0 to 4 or av dd . i injpm digital input pins per pin 4 ma total v ddmx b b. v ddmx : either v dd3x with x = 0 to 2 or v dd50 100 ma analog input pins per pin 4 ma total av dd 9ma positive overload current v in < xv ssnx c c. xv ssnx: either bv ss3x with x = 0 to 2, mv ss3x with x = 0 to 4, bv ss50 or av ss i injnm digital input pins per pin -4 ma total v ddmx b -100 ma analog input pins per pin -4 ma total av dd -9 ma
15 datasheet u18578ee1v0ds00 pd70f3461 1.2 capacitance connected to regcx the device requires to connect capacitors with t he following parameters to each of the pins regc30, regc31, regc32 and regc50 individually. note: the pins regc30, regc31, regc32 and re gc50 must not be loaded externally 1.3 i/o capactitances ta =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v table 1-3: external capacitance requirements for regcx parameter symbol conditi ons min. typ. max. unit capacitance c reg 3.3 4.7 10.0 f esr of capacitance c esr f0 = 100khz 0.6 table 1-4: i/o characteristics parameter symbol conditions min. typ. max. unit input capacitance c i fc = 1mhz unmeasured pins returned to 0 10 pf input/output capacitance, all i/o pins c io 15 pf
16 datasheet u18578ee1v0ds00 pd70f3461 2. electrical specification : device clock specifications 2.1 main oscillator characteristics ta =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v figure 2-1: main oscillator recommendations remark: values of capacitors c 1 , c 2 and the resistor r depend on used crystal and must be speci- fied in cooperation with the manufacturer. cautions: 1. external clock input is prohibited. 2. wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. ? place the oscillation circuit as close as possible to x1 and x2 pins. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating cur- rent flows. ? always make the ground point of the o scillator capacitor the same potential as cv ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. table 2-1: main oscillator operating conditions parameter symbol conditions min. typ. max. unit oscillation frequency f osc 16 a a. with any other frequency peripheral function can?t be guaranteed mhz oscillation stabilization time b b. t ost depends on the external crystal note: please specify the oscillation stabiliz ation time of the main oscillator t ost with the manufacturer of the external quartz crystal. t ost osc mode 10 ms x1 x2 c 1 c 2 r
17 datasheet u18578ee1v0ds00 pd70f3461 2.2 sub-oscillator characteristics ta =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v figure 2-2: sub-oscillator recommendations remark: values of capacitors c s1 , c s2 and resistor r s depend on used crystal and must be speci- fied in cooperation with the manufacturer. cautions: 1. external clock input is prohibited. 2. wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. ? place the oscillation circuit as clos e as possible to x1 and x2 pins. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating cur- rent flows. ? always make the ground point of the oscillator capacitor the same potential as cv ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. note: please specify the oscillation stabilization time for the sub-os cillator tsost wit h the manufac- turer of the external quartz crystal. table 2-2: sub-oscillator operating conditions parameter symbol conditions min. typ. max. unit oscillation frequency f sosc 32.500 32.768 33.000 khz xt1 xt2 c s1 c s2 r s
18 datasheet u18578ee1v0ds00 pd70f3461 2.3 peripheral pll characteristics ta =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v 2.4 cpu pll characteristics ta =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v 2.5 low-frequency internal oscillator characteristics ta =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v table 2-3: peripheral pll characteristics parameter symbol conditions min. typ. max. unit peripheral pll lock-up time t plt osc mode 400 s peripheral pll output period jitter a a. t popj is not tested in production. it is spec ified by design and ensured by evaluation. t popj -100 100 ps table 2-4: cpu pll characteristics parameter symbol conditions min. typ. max. unit cpu pll lock-up time t clt osc mode 400 s cpu pll output period jitter a a. t copj is not tested in production. it is spec ified by design and ensured by evaluation. t copj -100 100 ps table 2-5: cpu pll characteristics parameter symbol conditions min. typ. max. unit low-frequency internal oscillator frequency f lfiosc 120 240 480 khz low-frequency internal oscillator stabilization time a a. t lfrost is not tested in production. it is specif ied by design and ensured by evaluation. t lfiost 20 s
19 datasheet u18578ee1v0ds00 pd70f3461 2.6 high-frequency internal oscillator characteristics ta =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v 2.7 cpu clock ta =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v 2.8 pll clock t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v table 2-6: cpu pll characteristics parameter symbol conditions min. typ. max. unit high-frequency internal oscillator frequency f hfiosc 5.88 6.78 8.00 mhz high-frequency internal oscillator stabilization time a a. t hfrost is not tested in production. it is spec ified by design and ensured by evaluation. t hfiost 200 s table 2-7: cpu clock frequency clock mode symbol conditions min. typ. max. unit osc mode, pll 80 mhz table 2-8: pll clock frequency clock mode symbol conditions min. typ. max. unit peripheral clock f perph 80 mhz
20 datasheet u18578ee1v0ds00 pd70f3461 3. electrical specificati on : dc characteristics 3.1 general dc characteristics t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v table 3-1: input leakage current parameter symbol pin group conditions min. typ. max. unit input leakage current, high i lih1 1 0 v i bv dd3x 3a i lih2 2 0 v i bv dd30 2a i lih3 3 0 v i bv dd31 3a i lih4 4 0 v i bv dd32 3a i lih5 5 0 v i mv dd3x 3a i lih6 6 0 v i bv dd31 500 a a. high input current is caused by permanent pull-down resistor at the input. a i lih8 8 0 v i av dd 3a i lih10 10 0 v i v dd50 3a i lih11 11 0 v i v dd50 3a i lih13 13 0 v i v dd50 3a input leakage current, low i lil1 1 0 v i bv dd3x -3 a i lil2 2 0 v i bv dd30 -2 a i lil3 3 0 v i bv dd31 -3 a i lil4 4 0 v i bv dd32 -3 a i lil5 5 0 v i mv dd3x -3 a i lil6 6 0 v i mv dd31 -3 a i lil8 8 0 v i av dd -3 a i lil10 10 0 v i v dd50 -3 a i lil11 11 0 v i v dd50 -3 a i lil13 13 0 v i v dd50 -3 a
21 datasheet u18578ee1v0ds00 pd70f3461 3.2 input/output level of pin groups following conditions are va lid for all listed pin gr oup input/output level: -t a =-40 to +105c -v dd5x = 4.5 to 5.5v -v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v -v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v note: internally all bv dd3x (x=0 to 2) and mv dd3y (y= 0 to 4) are connected. all mentioned supply pins in this chapter has to be seen as main contribution and not as single supply! 3.2.1 input/output level pin group 1: main area general purpose ports these pins are supplied with bv dd3x with the same i/o characteristics. pins of this pin group are: ? group 1a (supplied by bv dd30 ): - p00 to p07 -p46 - p10 to p14 ? group 1b (supplied by bv dd31 ): - p40 to p44 - p81 to p84 ? group 1c (supplied by bv dd32 ): - p30 to p37 -p45 - p50 to p53 3.2.2 input/output level pin group 2: medialb ports these pins are supplied with b vdd30 with special medialb buffer characteristics. pins of this pin group are: - p15 to p17 table 3-2: input/output level pin group 1 parameter symbol conditions min. typ. max. unit input voltage,high v ih1 0.7 x bv dd3x bv dd3x +0.3 v input voltage,low v il1 -0.5 0.3 x bv dd3x v output voltage, high v oh1 i oh = -3ma bv dd3x -1.0 v output voltage, low v ol1 i ol = 3ma 0.4 v pull-up resistor a a. soft pull-up resistor r pu1 10 50 100 k table 3-3: input/output level pin group 2 parameter symbol conditions min. typ. max. unit input voltage,high v ih2 1.7 bv dd30 +0.3 v input voltage,low v il2 -0.5 0.7 v output voltage, high v oh2 i oh = -6ma 2.0 v output voltage, low v ol2 i ol = 6ma 0.4 v pull-up resistor a a. soft pull-up resistor r pu2 10 50 100 k
22 datasheet u18578ee1v0ds00 pd70f3461 3.2.3 input/output level pin group 3: flexray ports these pins are supplied with bv dd31 with the same i/o characteristics. pins of this pin group are: - p20 to p27 3.2.4 input/out put level pin group 4: mreset pin these pins are supplied with bv dd32 with the same i/o characteristics. pin of this pin group is: - mreset 3.2.5 input/output level pin group 5: external bus interface ports these pins are supplied with mv dd3x with the same i/o characteristics. pins of this pin group are: ? group 5a (supplied by mv dd30 ): -pcs0 - pct4 to pct6 - pdl0 to pdl3 ? group 5b (supplied by mv dd31 ): - pdl4 to pdl11 ? group 5c (supplied by mv dd32 ): - pdl12 to pdl15 - pal0 to pal3 ? group 5d (supplied by mv dd33 ): - pal4 to pal11 ? group 5e (supplied by mv dd34 ): - pal12 to pal15 - pah0 to pah3 -pcs1 -flmd1 table 3-4: input/output level pin group 3 parameter symbol conditions min. typ. max. unit input voltage,high v ih3 0.7 x bv dd31 bv dd31 +0.3 v input voltage,low v il3 -0.5 0.3 x bv dd31 v output voltage, high v oh3 i oh = -3ma bv dd31 -1.0 v output voltage, low v ol3 i ol = 3ma 0.4 v pull-up resistor a a. soft pull-up resistor r pu3 10 50 100 k table 3-5: input/output level pin group 4 parameter symbol conditions min. typ. max. unit input voltage,high v ih4 0.8 x bv dd32 bv dd32 +0.3 v input voltage,low v il4 -0.5 0.2 x bv dd32 v
23 datasheet u18578ee1v0ds00 pd70f3461 3.2.6 input/output level pin group 6: input-only port p80 this pin is supplied with bv dd31 . pin of this pin group is: - p80, this pin is shared with n-wire reset (drst) 3.2.7 input/output level pin group 10: isolated area general purpose ports these pins are supplied with v dd50 with the same i/o characteristics. pins of this pin group are: - p60 to p63 -wdtout -regon table 3-6: input/output level pin group 5 parameter symbol conditions min. typ. max. unit input voltage,high v ih5 0.7 x mv dd3x mv dd3x +0.3 v input voltage,low v il5 -0.5 0.3 x mv dd3x v output voltage, high v oh5 i oh5 = -3ma mv dd3x -1.0 v output voltage, low v ol5 i ol5 = 3ma 0.4 v pull-up resistor a a. soft pull-up resistor r pu5 10 50 100 k table 3-7: input/output level pin group 6 parameter symbol conditions min. typ. max. unit input voltage,high v ih6 0.7 x bv dd3x bv dd3x +0.3 v input voltage,low v il6 -0.5 0.3 x bv dd3x v pull-down resistor a a. permanent pull-down resistor r pd6 10 50 100 k table 3-8: input/output level pin group 10 parameter symbol conditions min. typ. max. unit input voltage,high v ih10 0.7 x v dd50 v dd50 +0.3 v input voltage,low v il10 -0.5 0.3 x v dd50 v output voltage, high v oh10 i oh = -3ma v dd50 -1.0 v output voltage, low v ol10 i ol = 3ma 0.4 v pull-up resistor a a. soft pull-up resistor r pu10 10 30 100 k
24 datasheet u18578ee1v0ds00 pd70f3461 3.2.8 input/output level pin group 11: isolated reset pin these pins are supplied with v dd5x with the same i/o characteristics. pin of this pin group is: - reset 3.2.9 input/output level pin group 13: isolated area flmd0 these pins are supplied with v dd5x with the same i/o characteristics. pin of this pin group is: -flmd0 3.3 supply current t a =-40 to +105c v dd50 = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v table 3-9: input/output level pin group 11 parameter symbol conditions min. typ. max. unit input voltage,high v ih11 0.8 x v dd50 v dd50 +0.3 v input voltage,low v il11 -0.5 0.25 x v dd50 v table 3-10: input/output level pin group 13 parameter symbol conditions min. typ. max. unit input voltage,high v ih13 0.8 x v dd50 v dd50 +0.3 v input voltage,low v il13 -0.5 0.2 x v dd50 v table 3-11: power supply current parameter conditions supply pins a a. n= 0 to 2 symbol min. typ. b b. the typical value refers to ta = 25c, v dd50 = 5v and v dd3n = 3.3v max. unit supply current c c. the port output current resulting from built-in pull-up or pull-down resi stances is not included. run mode (f cpu = 80mhz, pll: on) t a = 85c vdd3n i dd1ma 170 210 ma t a = 105c 260 ma t a = 105c vdd50 i dd1ia 1.2 ma idle mode (f osc = 16mhz) vdd3n i dd4ma 65 ma power down mode main area power-off isolated area stand-by t a = 25c vdd50 i dd5ia 55 a t a = 85c 300 a t a = 105c 600 a
25 datasheet u18578ee1v0ds00 pd70f3461 3.4 injected current 3.4.1 dc characteristics of overload current t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v 3.4.2 a/d converter influenced by injected current on adjacent pin t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v table 3-12: injected current: dc characteristics of overload current parameter symbol conditions min. typ. max. unit positive overload current v in > xv ddn a a. xv ddnx : either bv dd3x with x = 0 to 2, mv dd3x with x = 0 to 4 or av dd . i injp digital input pins per pin 1 ma total v ddmx b b. v ddmx : either v dd3x with x = 0 to 2 or v dd50 16 ma analog input pins per pin 1 ma total av dd 4ma positive overload current v in < xv ssnx c c. xv ssnx: either bv ss3x with x = 0 to 2, mv ss3x with x = 0 to 4, bv ss50 or av ss i injnm digital input pins per pin -1 ma total v ddmx b -16 ma analog input pins per pin -0.1 ma total av dd -1 ma table 3-13: injected current: dc characteristics of overload current parameter symbol conditions min. typ. max. unit degradation of overall error a a. these specifications are not tested in the outgoing inspection, but specified based on the device character- ization i injpad b b. measurement condition: current is injected into one pi n of the dut. measurement of effect of this injected current is measured at adjacent pin. caution: the value given in table 3-13 stands for the degration by injected current on an adja- cent pin. therefore, this value is added to the specification of a/d converters overall error defined seperatly as the electrical sp ecifications (5. ?electrical specification : ad converter? on page 47) if there is an increase leakage current, based on the negative currents injected into the pin adjacent to the converted channel, the effect on the a/d converters accuracy depends on the external analog source impedance. 5 lsb i injnad 5 lsb
26 datasheet u18578ee1v0ds00 pd70f3461 4. electrical specificati on : ac characteristics ac test input measurement points , v ih = 0.7 x v ddxy v il = 0.3 x v ddxy ac test output measurement points v oh = 0.7 x v ddxy v ol = 0.3 x v ddxy load conditions caution: if the load capacitance exceeds 50 pf due to the circuit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means. measurement points v ih v il v ih v il measurement points v oh v ol v oh v ol dut load on test c l =50pf
27 datasheet u18578ee1v0ds00 pd70f3461 4.1 reset of main area: mreset timing t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v figure 4-1: mreset timing figure 4-2: mreset delay during vdd ramp-up table 4-1: turning on / interception timing parameter symbol conditions min. typ. max. unit mreset high-level width a a. this signal high time is needed to ensure that the internal mreset release operation starts. t wmrsh 200 ns mreset low-level width b b. this signal low time is needed to ensure that the internal mreset is activated. reset pulses shorter than the given value may not be recognized by the device t wmrslil 200 ns mreset pulse rejection c c. the mreset input incorporates an analog filter. pulses shorter than this value will be ignored. characteristic is not tested during production, it is ensured by design and will be evaluated. t wmrrj 50 100 200 ns mreset power up delay d d. during ramp-up of the internal power supply (vdd of the main area) the release of mreset has to be delayed until vdd and the main oscillato r are stabilized. please also refer to chapter 2.1 on page 16. t wmrpd 2 + t ost ms t wmrsh t wmrsl mreset regc3x mreset t wmrpd t wmrgd vdd3x
28 datasheet u18578ee1v0ds00 pd70f3461 4.2 reset of isolated area: reset timing t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v figure 4-3: reset timing figure 4-4: reset delay during vdd ramp-up table 4-2: turning on / interception timing parameter symbol conditions min. typ. max. unit reset high-level width a a. this signal high time is needed to ensure th at the internal reset release operation starts. t wrsh 300 ns reset low-level width b b. this signal low time is needed to ensure t hat the internal reset is activated. t wrslil 300 ns reset pulse rejection c c. the reset input incorporates an analog filter. pulses shorter th an this value will be ignored. char- acteristic is not tested during production, it is ensured by design an d will be evaluated. t wrrj 140 200 350 ns reset power up delay d d. during ramp-up of the internal power supply (vdd of the ma in area) the release of reset has to be delayed until vdd is stabilized. t wrpd 2ms t wrsh t wrsl reset vdd5x reset t wrpd
29 datasheet u18578ee1v0ds00 pd70f3461 4.3 interrupt timing t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v remark: n = 0 to 14 figure 4-5: interrupt timing table 4-3: interrupt timing parameter symbol conditions min. max. unit nmi input high level width a a. pulses longer than this value will pass hte analog filter t nih 150 ns nmi input low level width a t nil 150 ns nmi pulse rejection b b. pulses shorter than this value do not pass the analog input filter. this characte ristic is not tested in production, it is ensured by design and evaluated. t nirj 50 150 ns intpn input high level width a t ith 150 - intpn input low level width a t itl 150 ns intpn pulse rejection b t itrj 50 150 - nmi intpn
30 datasheet u18578ee1v0ds00 pd70f3461 4.4 clocked serial interface b (csib) characteristics t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v table 4-4: csib characteristics (master mode) remark: n = 0, 1 table 4-5: csib characteristics (slave mode) remark: n = 0, 1 cbnsck2 to cbnsck0 111b parameter symbol min. max. unit sckbn output clock cycle time t cyskm 125 ns sckbn output high level width t wskhm 0.5 t cyskm - 10 ns sckbn output low level width t wsklm 0.5 t cyskm - 10 ns sibn input setup time (vs. sckbn )t ssiskm 20 ns sibn input hold time (vs. sckbn )t hsksim 10 ns sobn output delay (vs. sckbn ) t dsksom 10 ns sobn output hold time (vs. sckbn )t hsksom 0.5 t cyskm - 10 ns cbnsck2 to cbnsck0 = 111b parameter symbol min. max. unit sckbn input clock cycle time t cysks 125 ns sckbn input high level width t wskhs 0.5 t cyskm - 10 ns sckbn input low level width t wskls 0.5 t cyskm - 10 ns sibn input setup time (vs. sckbn )t ssisks 5ns sibn input hold time (vs. sckbn )t hsksis 10 ns sobn output delay (vs. sckbn ) t dsksos 25 ns sobn output hold time (vs. sckbn )t hsksos t wskhs ns
31 datasheet u18578ee1v0ds00 pd70f3461 figure 4-6: csib timing in master mode (ckp, dap bits = 00b or 11b) figure 4-7: csib timing in master mode (ckp, dap bits = 01b or 10b) figure 4-8: csib timing in slave m ode (ckp, dap bits = 00b or 11b) t cyskm t wsklm t dsksom t hsksom t ssiskm t hsksim t wskhm sckbn sobn sibn t cyskm t wskhm t dsksom t hsksom t ssiskm t hsksim t wsklm sckbn sobn sibn t cysks t wskls t dsksos t hsksos t ssisks t hsksis t wskhs sckbn sobn sibn
32 datasheet u18578ee1v0ds00 pd70f3461 figure 4-9: csib timing in slave mode (ckp, dap bits = 01b or 10b) t cysks t wskhs t dsksos t hsksos t ssisks t hsksis t wskls sckbn sobn sibn
33 datasheet u18578ee1v0ds00 pd70f3461 4.5 enhanced queued clocked serial interface (csie) timing t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v cautions: 1. all output pins used for csie application (csie0 [ports p40, p41] and csie1 [pdl14, pdl15] are connected to an external load of 50pf. 2. all chip select output pins for the csie (scse00 to 07 [pal7 to 14] and scse10 to 13 [pal3 to 6] are connected to an external load of 25pf. figure 4-10: csie ac load condition table 4-6: csie characteristics (master mode) parameter symbol min. max. unit macro operation clock, cycle time t kcy 31.25 ns scken cycle time t kcym 125 ns scken high level width t kwhm t kcym /2 - 10 ns scken low level width t kwlm t kcym /2 - 10 ns sien input setup time (vs. scken )t ssi 20 ns sien input hold time (vs. scken )t hsim 10 ns soen output delay (vs. scken )t dsom 20 ns soen output hold time (vs. scken )t hsom t kcym /2 - 10 ns scsenm inactive (high) width censit=x cenope=0 cenmd=x t wscsb0 t kcym /2 - 10 ns censit=x cenope=1 cenmd=x t wscsb1 (cs idle + 0.5)*t kcym - 10 ns dut csie application load c l =50pf (sien, sclkn) c l =25pf (scsce00 to 07, scsce10 to 13) c l
34 datasheet u18578ee1v0ds00 pd70f3461 remark: n=0,1 m=7-0(n=0),3-0(n=1) cs setup ,cs inter : are set by register cenopt0 cs idle ,cs hold : are set by register cenopt1 scsenm setup time (vs. scken ) censit=x cenope=0 cenidl=x cenmd=0 t sscsb0 t kcy - 10 ns censit=x cenope=1 cenidl=0 cenmd=0 t sscsb1 t kcym + t kcy - 10 ns censit=x cenope=0 cenwe=1 cencsm=1 cenidl=x cenmd=x t sscsb2 t kcym / 2 + t kcy - 10 ns censit=x cenope=1 (cenidl=0 and cs change) cenmd=x cs setup *t kcym + t kcy - 10 ns censit=x cenope=1 cenidl=1 cenmd=x scsenm hold time (vs. scken ) censit=0 cenope=0 cenmd=x t hscsb0 t kcy - 10 ns censit=1 cenope=0 cenmd=x t hscsb1 t kcym /2 + t kcy - 10 ns censit=0 cenope=1 cenmd=x t hscsb2 cs hold *t kcym + t kcy - 10 ns censit=1 cenope=1 cenmd=x t hscsb3 (cs hold + 0.5)* t kcym + t kcy - 10 ns scsenm interframe time censit=x cenope=1 cenmd=x t inter cs inter *t kcym - 5 ns censit=x cenope=0 cenmd=x - not applicable ns table 4-6: csie characteristics (master mode) parameter symbol min. max. unit
35 datasheet u18578ee1v0ds00 pd70f3461 remark: n= 0,1 table 4-7: csie characteristics (slave mode) parameter symbol min. max. unit macro operation clock, cycle time t kcy 31.25 ns scken cycle time t kcys 125 ns scken high level width t kwhs t kcys /2 - 10 ns scken low level width t kwls t kcys /2 - 10 ns sien input setup time (vs. scken )t ssis 10 ns sien input hold time (vs. scken )t hsis t kcy x 1.5 +10 ns soen output delay (vs. scken )t dsos 20 ns soen output hold time (vs. scken )t hsos t kcys /2 - 10 ns
36 datasheet u18578ee1v0ds00 pd70f3461 figure 4-11: csien timings (a) [ scken /sien/soen] pins in master mode: (cenctl1: cenckp/cendap=0/0 or 1/1) remark: n= 0-1 (b) [ scken /sien/soen] pins in master mode: (cenctl1: cenckp/cendap=1/0 or 0/1) remark: n= 0-1 scken soen sien clock scken soen sien
37 datasheet u18578ee1v0ds00 pd70f3461 (c) [ scken /sien/soen] pins in slave mode: (c enctl1: cenckp/cendap=0/0 or 1/1) remark: n= 0-1 (d) [ scken /sien/soen] pins in slave mode: (c enctl1: cenckp/cendap=1/0 or 0/1) remark: n= 0-1 scken scken
38 datasheet u18578ee1v0ds00 pd70f3461 (e) only in master mode (cenctl0:c ensit=0 & cenctl4:cenope/cenmd=0/0) remark: n= 0-1 m= 7(n=0),3(n=1) cetnic: csien transfer end interrupt (f) only in master mode (cenctl0:c ensit=0 & cenctl4:cenope/cenmd=1/0) remark: n= 0-1 m= 7(n=0),3(n=1) cetnic: csien transfer end interrupt scsen[m-0] scken cetnic continuous transfer start (sn output timing) scsen[m-0] scken cetnic (sn output timing)
39 datasheet u18578ee1v0ds00 pd70f3461 (g) only in master mode (cenctl0:c ensit=0 & cenctl4:cenope/cenmd=1/1) remark: n= 0-1 m= 7(n=0),3(n=1) cetnic: csien transfer end interrupt (h) only in master mode (cenctl0:c ensit=1 & cenctl4:cenope/cenmd=0/0) remark: n= 0-1 m= 7(n=0),3(n=1) cetnic: csien transfer end interrupt scsen[m-0] scken cetnic (sn output timing) scsen[m-0] scken cetnic (sn output timing)
40 datasheet u18578ee1v0ds00 pd70f3461 (i) only in master mode (cenctl0:censit=1 & cenctl4:cenope/cenmd=1/0) remark: n= 0-1 m= 7(n=0),3(n=1) cetnic: csien transfer end interrupt (j) only in master mode (cenctl0:censit=1 & cenctl4:cenope/cenmd=1/1) remark: n= 0-1 m= 7(n=0),3(n=1) cetnic: csien transfer end interrupt scsen[m-0] scken cetnic (sn output timing) scsen[m-0] scken cetnic (sn output timing)
41 datasheet u18578ee1v0ds00 pd70f3461 4.6 i 2 c characteristics t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v table 4-8: i 2 c characteristics parameter symbol normal mode fast mode unit min. max. min. max. scl0 clock frequency f clk 0 100 0 400 khz bus-free time (between stop/start conditions) t buf 4.7 1.3 s hold time a a. at the start condition, the first clock pu lse is generated after the hold time. t hd:sta 4.0 0.6 s scl0 clock low-level width t low 4.7 1.3 s scl0 clock high-level width t high 4.0 0.6 s setup time for start/restart conditions t su:sta 4.7 0.6 s data hold time cbus compatible master t hd:dat 5.0 s i 2 c mode 0 b b. the system requires a minimum of 300ns hold time internally for the sda signal (at v ihmin of scl0 signal) in order to occupy the undefined area at falling edge of scl0. 3.45 c c. if the system does not extend the scl0 signal low time (t low ), only the maximum data hold time (t hd:dat ) needs to be satisfied. 0 b 0.9 c s data setup time t su:dat 250 100 d d. the fast-speed-mode iic bus can be used in a normal-mode iic bus system. in this case, set the fast-speed-mode iic bus so that it meets the following conditions: - if the system does not extend th e scl0 signals low state hold time: t su:dat 250ns - if the system extends the scl0 signal low state hold time: transmit the following data bit to the sda0 line prior to releasing the scl0 line (t rmax + t su:dat = 1000+250 ns = 1250ns : normal mode iic bus specification). ns stop condition setup time t su:sto 4.0 0.6 s noise suppression e e. noise suppresion is only available in fast-speed mode. t sp t iiclk f f. t iiclk is the period of the iiclk supplied by the clock controller. s capacitive load of each bus line c b 400 400 pf
42 datasheet u18578ee1v0ds00 pd70f3461 figure 4-12: i 2 c timing scl0 p t su: s ta t hd: s ta t low t hi g h t buf sda0 t sp t r t hd: d at t f t su: d at s t hd: s ta sr p t su: s to
43 datasheet u18578ee1v0ds00 pd70f3461 4.7 uartd timing t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v 4.8 can timing t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v 4.9 flexray timing t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v table 4-9: uartd timing parameter symbol conditions min. max. unit transfer rate t uartdn 312.5 kbps table 4-10: can timing parameter symbol conditions min. max. unit transfer rate t afcan 1 mbps table 4-11: flexray timing parameter symbol conditions min. max. unit transfer rate t flexray 10 mbps
44 datasheet u18578ee1v0ds00 pd70f3461 4.10 medialb timing t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v the ac characterics of the medialb of following tabl e is considered with a load capaticance of 40 pf. table 4-12: medialb timing parameter symbol conditions min. typ. max. unit mlbclk operating frequencies f mck 256 x fs at 44.0 khz 11.264 mhz 256 x fs at 48.0 khz 12.228 512 x fs at 44.0 khz 24.576 512 x fs at 48.1 khz 24.627 512 x fs pll unlocked 25.600 mlbclk rise time t mckr 3ns mlbclk fall time t mckf 3ns mlbclk cycle time t mckc 256 x fs 81 ns 512 x fs 40 mlbclk low time t mckl 256 x fs 31.5 37 ns 256 x fs pll unlocked 30 35.5 512 x fs 14.5 17 ns 512 x fs pll unlocked 14 16.5 mlbclk high time t mckh 256 x fs 31.5 38 ns 256 x fs pll unlocked 30 36.5 512 x fs 14.5 17 ns 512 x fs pll unlocked 14 16.5 mlbclk pulse width variation t mpwv a a. pulse width variation is measured at 1.25v by triggering on one edge of mlbclk and measuring the spread on the other edge, measured in ns peak-to-peak (pp) 2ns pp mlbsig/mlbdat input valid (vs. mlbclk falling) t dsmcf 1ns mlbsig/mlbdat input hold (vs. mlbclk low) t dhmcf 0ns mlbsig/mlbdat output high impedance (vs. mlbclk low) t mcfdz 0 t mckl ns bus hold time t mdzh 4ns mlbsig/mlbdat output valid (vs. mlbclk rising) t dsmch 13 ns
45 datasheet u18578ee1v0ds00 pd70f3461 figure 4-13: medialb timing figure 4-14: medialb puls e width variation timing mlbsig/ mlbdat (input) valid mlbclk t mckr t mckh t mckc t dsmcf t dhmcf t mckf t mckl valid mlbsig/ mlbdat (output) t mcfdz t mdzh t dsmch mlbclk t mpwv t mpwv
46 datasheet u18578ee1v0ds00 pd70f3461 4.11 timer aa timing t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v remark: m = 0 to 3 ; n = 0,1 figure 4-15: timer aa input timing 4.12 timer ab timing t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v remark: m = 0, 1 ; n = 0 to 3 figure 4-16: timer ab input timing table 4-13: timer aa timing parameter symbol conditions min. typ. max. unit tiaamn high-level width t tiaahnb react on both edges 150 ns t tiaahns react on single edge 150 ns tiaamn low-level width t tiaalnb react on both edges 150 ns t tiaalns react on single edge 150 ns table 4-14: timer ab timing parameter symbol conditions min. typ. max. unit tiabmn high-level width t tiabhnb react on both edges 150 ns t tiabhns react on single edge 150 ns tiabmn low-level width t tiablnb react on both edges 150 ns t tiablns react on single edge 150 ns tiaamn t tiaah t ti a al tiabmn t tiabh t ti a bl
47 datasheet u18578ee1v0ds00 pd70f3461 5. electrical specification : ad converter t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v table 5-1: ad converter parameter symbol condi tions min. typ. max. unit resolution 10 bit reference volatge av ss av dd v overall error a a. the quantization error of 0.5 lsb is not included. toe av ss ain av ref0 = av dd 4 lsb quantization error 0.5 lsb conversion time b b. the conversion time only in the analog part. the conversion time depends on register setting admn1. for admn1 register setting please refer to the users manual t conv 2.0 20.0 s analog input voltage v ian av ss av ref v analog input equivalent circuit resistance c c. these values are not tested during production. they are ensured by design and evaluated. r ina 0.5 0.8 k analog input equivalent circuit capacitance c c ina 10 12 pf analog supply current i avdd 1.5 3 ma analog reference supply current d d. the analog reference supply current is mainly transi ent current, which is influenced by the conversion time. the given value is not tested during producti on. it is ensured by design and evaluated. i avref 60 150 a
48 datasheet u18578ee1v0ds00 pd70f3461 6. electrical specifi cation : flash memory characteristics 6.1 code flash memory characteristics 6.1.1 code flash general characteristics t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v table 6-1: code flash general characteristics 6.1.2 code flash self-programming characteristics over lifetime t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v cautions: 1. the values given in table 6-2 are only valid for a cpu frequency of 80mhz. 2. the following pre-compile option was used to determine these values: status_check_user (in selflibsetup.h) table 6-2: code flash self-programming characteristics over lifetime parameter symbol conditions min. typ. max. unit number of rewrites c cfwrt 1000 times data retention t cfret 15 years write current (dc) a a. total 3v dc current of the code flash which is supplied by pins v dd30 , v dd31 and v dd32 . i cfwrt 30 ma erase current (dc) a i cfer 28 ma parameter symbol conditions min. typ. max. unit blank check time t cflbl,4k one memory block (4k) 0.66 0.79 ms t cfvbl,256k 64 memory blocks (256k) 21.67 26.00 ms erase time t cfler,4k one memory block (4k) 13.97 279.40 ms t cfler,256k 64 memory blocks (256k) 34.76 695.20 ms write time t cflwr,2w write two words a a. the corresponding library call is configured for 2 words per call. 0.33 1.10 ms t cflwr,4k one memory block (4k) @ 256 bytes b b. the corresponding library call uses a 256 bytes (= 64 words) source buffer. 29.48 423.72 ms internal verify time t cflvr,4k one memory block (4k) 2.86 3.43 ms t cflvr,256k 64 memory blocks (256k) 171.38 205.66 ms
49 datasheet u18578ee1v0ds00 pd70f3461 6.1.3 code flash end-of-line on-board programming characteristics (pg-fp4: csi) t a =-40 to +40c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v table 6-3: code flash end-of-line on-board programming characteristics (pg-fp4: csi) note: the specified value does not include the time ne eded to establish the c onnection to the device. 6.1.4 code flash end-of-line self-programming characteristics t a =-40 to +40c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v cautions: 1. the values given in table 6-4 are only valid for a cpu frequency of 80mhz. 2. the following pre-comp ile option was used to determine these values: status_check_user (in selflibsetup.h) table 6-4: code flash end-of-line self-programming characteristics parameter a a. all parameters apply to the code flash area, i.e. all code flash blocks (0 to 127). symbol conditions min. typ. max. unit blank check time t cfecbl w/e cycles 5 f osc = 16mhz f csiclk = 2.5mhz 0.08 0.10 s erase time t cfecer 0.20 0.40 s write time t cfecwr 13 22 s read verify time t cfecvr 810s parameter symbol conditions min. typ. max. unit blank check time t cflbl,4k one memory block (4k) 0.66 0.79 ms t cfvbl,256k 64 memory blocks (256k) 21.67 26.00 ms erase time t cfler,4k one memory block (4k) 13.97 55.88 ms t cfler,256k 64 memory blocks (256k) 34.76 139.04 ms write time t cflwr,2w write two words a a. the corresponding library call is configured for 2 words per call. 0.33 0.50 ms t cflwr,4k one memory block (4k) @ 256 bytes b b. the corresponding library call uses a 256 bytes (= 64 words) source buffer. 29.48 117.09 ms internal verify time t cflvr,4k one memory block (4k) 2.86 3.43 ms t cflvr,256k 64 memory blocks (2 56k) 171.38 205.66 ms
50 datasheet u18578ee1v0ds00 pd70f3461 6.2 data flash memory characteristics 6.2.1 data flash general characteristics t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v table 6-5: data flash general characteristics 6.2.2 data flash self-programmi ng characteristics over lifetime t a =-40 to +105c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v cautions: 1. the values given in table 6-6 are only valid for a cpu frequency of 80mhz. 2. the following pre-compile option was used to determine these values: status_check_user (in selflibsetup.h) table 6-6: data flash self-progra mming characteristics over lifetime parameter symbol conditions min. typ. max. unit size of one data flash section s dfs 2 kbytes number of data flash sections c dfs 16 sections number of rewrites of one data flash section c dfwrt 10000 times data retention t dfret after 1000 rewrite cycles 15 years after 10000 rewrite cycles 5 years write current (dc) a a. total 3v dc current of the data flash which is supplied by pins v dd30 , v dd31 and v dd32 . i dfwrt 15 ma erase current (dc) a i dfer 14 ma parameter symbol conditions min. typ. max. unit blank check time a a. scales approximately linear with the number of memory blocks checked. t dflbl,2k one memory block (2k) 0.39 0.47 ms erase time b b. values increase only slightly if two, four, eight memory blocks are erased. t dfler,2k 13.46 269.15 ms write time t dflwr,1w write one word 0.13 1.54 ms t dflwr,4w write four words 0.25 5.89 ms internal verify time c c. scales approximately linear with the number of memory blocks verified. t dflvr,2k one memory block (2k) 2.71 3.26 ms
51 datasheet u18578ee1v0ds00 pd70f3461 6.2.3 data flash end-of-line on-board programming characteristics (pg-fp4: csi) t a =-40 to +40c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v table 6-7: data flash end-of-line on-board programming characteristics (pg-fp4: csi) note: the specified value does not include the time ne eded to establish the c onnection to the device. 6.2.4 data flash end-of-line self-programming characteristics t a =-40 to +40c v dd5x = 4.5 to 5.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v w/e cycles 5 table 6-8: data flash end-of-line self-programming characteristics note: the specified value does not include the time ne eded to establish the c onnection to the device. parameter a a. all parameters apply to the data flash area, i.e. all code flash blocks (0 to 15). symbol conditions min. typ. max. unit blank check time t dfecbl w/e cycles 5 f osc = 16mhz f csiclk = 2.5mhz 0.01 0.02 s erase time t dfecer 0.20 0.40 s write time t dfecwr 24s read verify time t dfecvr 12s parameter a a. all parameters apply to the data flash area, i.e. all code flash blocks (0 to 15). symbol conditions min. typ. max. unit blank check time b b. scales approximately linear with t he number of memory blocks checked. t dfesbl,2k one memory block (2k) 0.39 0.47 ms erase time c c. values increase only slightly if tw o, four, eight memory blocks are erased. t dfeser,2k 13.46 53.86 ms write time t dfeswr,1w write one word 0.13 0.44 ms t dfeswr,4w write four words 0.25 1.50 ms internal verify time d d. scales approximately linear with t he number of memory blocks verified. t dfesvr,2k one memory block (2k) 2.71 3.26 ms
52 datasheet u18578ee1v0ds00 pd70f3461 7. requirements for a supply voltage v dd50 below 4.5v all conditions given in the following sub-chapters have to be consider ed if the device shall be operated at the (low) supply voltage of v dd50 = 3.15 to 4.5v. all conditions mentioned in these chapters must be applied along with every other parameter that has been specified above, i.e. from chapter 1 to chapter 6. in case one of these parameter is mentioned in the following chapter it subtitutes the specif ication mentioned in ch apter 1 to chapter 6. in all conditions mentioned in chapter 1 to chapter 6 the statement vdd50 = 4.5 to 5.5v can be substi- tuted by the statement vdd50 = 3.15 to 4.5v while applying the specification mentioned below. for each parameter that is not mentione d in the present chapter, the specif ications of chapter 1 to chapter 6 remains valid. (1) absolute maximum ratings t a = -40 ~ 105c, operation modes: all duration: 15years v ss5x = bv ss = v ss3x = av ss0 = mv ss3x = 0v please notice! impo rtant to read! this chapter contains important pieces of information on the special require- ments for an extended range of operatin g voltage supply for the device for v dd50 : 3.15v to 4.5v table 7-1: absolute maximum ratings parameter symbol test conditions ratings unit operating ambient temperature t a normal operating mode -40 to +105 c storage temperature t stgb -40 to +125 c high level output current group 10 i oh10 1 pin -0.5 ma group 10 i oha10 total -1 ma low level output current group 10 i ol10 1 pin 0.5 ma group 10 i ola10 total 1 ma
53 datasheet u18578ee1v0ds00 pd70f3461 (2) general dc characteristics t a =-40 to +105c v dd5x = 3.15 to 4.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v (3) input/output level pin group 10: isolated area general purpose ports these pins are supplied with v dd50 with the same i/o characteristics. pins of this pin group are: - p60 to p63 -wdtout -regon (4) input/output level pin group 11: isolated reset these pins are supplied with v dd5x with the same i/o characteristics. pin of this pin group is: - reset table 7-2: pin leak current parameter symbol pin group conditions min. typ. max. unit input leakage current, high i lih10 10 0 v i v dd50 3a i lih11 11 0 v i v dd50 3a i lih13 13 0 v i v dd50 3a input leakage current, low i lil10 10 0 v i v dd50 -3 a i lil11 11 0 v i v dd50 -3 a i lil13 13 0 v i v dd50 -3 a table 7-3: input/output level pin group 10 parameter symbol conditions min. typ. max. unit input voltage,high v ih10 0.7 x v dd5x v dd5x +0.3 v input voltage,low v il10 -0.5 0.3 x v dd5x v output voltage, high v oh10 i oh = -0.5ma v dd5x -1.0 v output voltage, low v ol10 i ol = +0.5ma 0.4 v pull-up resistor a a. soft pull-up resistor r pu10 10 30 100 k table 7-4: input/output level pin group 11 parameter symbol conditions min. typ. max. unit input voltage,high v ih11 0.8 x v dd50 v dd5x +0.3 v input voltage,low v il11 -0.5 0.25 x v dd50 v
54 datasheet u18578ee1v0ds00 pd70f3461 (5) input/output level pin group 13: isolated area flmd0 these pins are supplied with v dd5x with the same i/o characteristics. pin of this pin group is: -flmd0 (6) supply current t a =-40 to +105c v dd50 = 3.15 to 4.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v (7) ac characteristic: reset timing t a =-40 to +105c v dd5x = 3.15 to 4.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v note: for figures please refer to 4.2 ?reset of isolated area: reset timing? on page 28 table 7-5: input/output level pin group 13 parameter symbol conditions min. typ. max. unit input voltage,high v ih13 0.8 x v dd50 v dd5x +0.3 v input voltage,low v il13 -0.5 0.2 x v dd50 v table 7-6: power supply current parameter conditions supply pins a a. n= 0 to 2 symbol min. typ. b b. the typical value refers to ta = 25c, v dd50 = 5v and v dd3n max. unit supply current c c. the port output current resulting from built-in pull-up or pull-down resi stances is not included. run mode (f cpu = 80mhz, pll: on) vdd50 i dd1ia 1.2 ma power down mode main area power-off isolated area stand-by t a = 25c vdd50 i dd5ia 55 a t a = 85c 300 a t a = 105c 600 a table 7-7: turning on / interception timing parameter symbol conditions min. typ. max. unit reset high-level width a a. this signal high time is needed to ensure th at the internal reset release operation starts. t wrsh 300 ns reset low-level width b b. this signal low time is needed to ensure t hat the internal reset is activated. t wrslil 300 ns reset pulse rejection c c. the reset input incorporates an analog filter. pulses shorter th an this value will be ignored. char- acteristic is not tested during production, it is ensured by design an d will be evaluated. t wrrj 140 200 350 ns reset power up delay d d. during ramp-up of the internal power s upply (vdd of the main area) the release of reset has to be delayed until vdd and the main oscill ator are stabilized. t wrpd 2ms
55 datasheet u18578ee1v0ds00 pd70f3461 (8) ac characteristic: interrupt timing t a =-40 to +105c v dd5x = 3.15 to 4.5v v dd3x = av dd = bv dd3x = mv dd3x = 3.0 to 3.6v v ss5x = v ss3x = av ss = bv ss5x = bv ss3x = mv ss3x = 0v notes: 1. these settings refer to intp13 a nd intp14 located on the isolated area 2. for figures please refer to 4.3 ?interrupt timing? on page 29 table 7-8: interrupt timing parameter symbol conditions min. max. unit intpn input high level width a a. pulses longer than this value will pass hte analog filter t ith 150 - intpn input low level width b b. pulses shorter than this value do not pass the analog input filter. this characte ristic is not tested in production, it is ensured by design and evaluated. t itl 150 ns intpn pulse rejection b t itrj 50 150 -
58 datasheet u18578ee1v0ds00 pd70f3461 8. package drawings figure 8-1: v850e/cag4-m note: copper lead frame with nipdau plating 108 73 136 109 144 72 37 144-pin plastic lqfp (fine pitch) (20x20) item millimeters note a 22.0 0.2 b 20.0 0.2 c 20.0 0.2 d f 1.25 22.0 0.2 s144gj-50-uen s 1.5 0.1 k 1.0 0.2 l 0.5 0.2 r3 ? + 4 ? - 3 ? g 1.25 h 0.22 0.05 i 0.08 j 0.5 (t.p.) m 0.17 n 0.08 p 1.4 q 0.10 0.05 + 0.03 - 0.07 each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. s s m detail of lead end i j f g h q r p k m l n cd s a b
59 datasheet u18578ee1v0ds00 pd70f3461 [memo]
60 datasheet u18578ee1v0ds00 pd70f3461 9. revision history this document is the first release of the v850cag4-m datasheet. the revision history of u18578ee1v0ds00 refers to the v8 50e/cag4-m electrical target specification ease-es-0009 v0.4. version chapter page remarks 1 12 ? specification for storage temperature in table 1-1 added v.1.0 2 16 ? max. value for t ost removed, replaced by typ. ? note regarding t ost added 17 ? specification for t sost removed from table 2-2 ? note regarding t sost added 18 cpu pll output period jitter added to table 2-4 3 25 chapter ?dc characteristics for pins influ enced by injected current on adjacent pin? removed 4 27 table 4-1: turning on / interception timing ? t wmrgd removed, not applicable, timing included in t wmrpd ? t wmrpd min. timing added 28 table 4-2: turning on / interception timing ? t wrpd min. timing added ? table footer d) reference to main o scillator removed; not applicable for reset 30 csib table 4-4 and table 4-5 timings added 33 csie timings ? caution regarding load added ? figure 4-12 csie ac load condition added 33 - 35 table 4-6 and table 4-7 timings added - chapter ?external asynchronous memory? removed 6 48-51 flash memory characteristics; complete chapter extended ? code flash memory characteristics ? data flash memory characteristics 7 52 ? specification for storage temperature in table 7-1 added ? restriction for use of 32khz sub- oscillator bellow 4.5v removed 54 table 7-7: turning on / interception timing ? t wrpd min. timing added
61 datasheet u18578ee1v0ds00 pd70f3461
62 datasheet u18578ee1v0ds00 pd70f3461 notes for cmos devices 1. precaution against esd for semiconductors strong electric field, when exposed to a mos de vice, can cause destruction of the gate oxide and ultimately degrade the device operat ion. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it on ce, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor device s must be stored and transported in an anti-static container, stat ic shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2. handling of unused input pins for cmos no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by us ing a pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd with a resistor, if it is co nsidered to have a possibility of being an output pin. all handling related to the un used pins must be judged device by device and related specifications governing the devices. 3. status before initialization of mos devices power-on does not necessarily define initial stat us of mos device. production process of mos does not define the initial operat ion status of the devic e. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be ex ecuted immediately after power-on for devices having reset function.
63 datasheet u18578ee1v0ds00 pd70f3461 legal notes ? the information in this document is current as of june 2008. the information is subject to change without notice. for actual design-in, refer to the late st publications of nec electronics data sheets or data books, etc., for the most up-to-date specif ications of nec electronics products. not all prod- ucts and/or types are available in every country. please check wit h an nec sales representative for availability and addi tional information. ? no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec electronics. nec electronics assumes no res ponsibility for an y errors that may appear in this document. ? nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such nec electronics products. no license, express, implied or otherwise, is granted under any patent s, copyrights or other intellec- tual property rights of nec electronics or others. ? descriptions of circuits, software and other related information in this document are provided for illustrative pur poses in semiconductor pr oduct operation a nd application exampl es. the incorpora- tion of these circuits, software and information in the design of customer's equipment shall be done under the full responsibilit y of customer. nec electronics assume s no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and informa- tion. ? while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be elimi- nated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customer s must incorporate sufficient safety measures in their design, such as redundancy, fire -containment and anti-failure features. ? nec electronics products are classified into the following three quality grades: ?standard?, ?spe- cial? and ?specific?. the "specific" quality grade applies only to nec electronics products developed based on a customer-designated ?quality assurance program? for a specific applicat ion. the recommended applications of nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electron ics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-cr ime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, s ubmersible repeaters, nuclear reactor control systems, life support systems and medi cal equipment for life support, etc. the quality grade of nec electronics products is ?s tandard? unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use ne c electronics products in applications not intended by nec electron ics, they must contact nec electronics sales representative in advance to de termine nec electronics 's willingne ss to support a given application. notes: 1. "nec electronics" as used in this statem ent means nec electronics corporation and also includes its majority-owned subsidiaries. 2. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). 3. superflash ? is a registered trademar k of silicon storage technol ogy, inc. in several coun- tries including the united states and japan. this product uses superflash ? technology licensed from silicon st orage technology, inc.
64 datasheet u18578ee1v0ds00 pd70f3461 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec o ffice in your country to obtain a list of authorized representatives an d distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of relate d technical literature ? development environment specifications (for exampl e, specifications for third-party tools and com- ponents, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 sucursal en espa?a madrid, spain tel: 091- 504 27 87 fax: 091- 504 28 60 succursale fran?aise vlizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. singapore tel: 65-6253-8311 fax: 65-6250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos, brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829
65 datasheet u18578ee1v0ds00 pd70f3461 [memo]

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